# ECE/CS 755, FALL 2002

Ηλεκτρονική - Συσκευές

2 Νοε 2013 (πριν από 4 χρόνια και 6 μήνες)

97 εμφανίσεις

ECE/CS 755, FALL 2002

Homework 1

Due Monday
October

14
th
, in class

1)

Consider a CMOS inverter with process parameters as given
below
.
Derive
analytic expressions for the propagation delay times t
P
LH

and t
PHL
.
Size the
transistors (calculate W/L ratio)

in

the inverter

to achieve
t
PHL

= t
PLH

= 3.6
ns
.
Assume a Load capacitance of 1pf.
(VDD = 5V).

Assume the following device
parameters:

V
Tn

= 0.6V,
V
Tp

=
-
0.8V,

n
C
OX

= 188.6


V

,

p
C
OX

= 65.4

V

2)

In
the
figure shown below assume the capacitor is initially charged and the input
‘S’ switches instantaneously from 0 to VDD. Derive an expression for the
fall

time. Clearly identify the operating regions of the tra
nsistors.

3)

Consider a CMOS inverter powered by a supply voltage of 5V. The channel
length of both the transistors is L
n

= L
p

= 0.6um.

Assume the device parameters
specified in problem 1.

a.

Determine the (W
n
/W
p
) ratio so that the switching threshold vo
ltage of the
circuit is V
INV

= 1.4V.

(Switching threshold voltage is defined as
V
INV
=V
IN
=V
OUT
.

b.

The
CMOS fabrication process used to manufacture this inverter allows a
variation of the V
Tn

value by 15% around its nominal value, and a
variation in V
Tp

value by 20% around its nominal value. Assuming that
all other parameters always retain their nominal values, find the upper and
lower limits of the switching threshold voltage of the inverter.

4)

Draw a stick diagram using Euler
-
path method fo
r the circuit

shown in the attached figure (Fig 8.25c of the text).