Design and Analysis of Low-Power 10-Transistor Full Adders Using Novel Gates

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Design and Analysis of Low
-
Power 10
-
Transistor Full Adders
Using Novel
XOR
-
XNOR

Gates



Matthew Quesada

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS
--
II:

ANALOG AND DIGITAL SIGNAL PROCESSING VOL. 49

NO. 1, JANUARY 2002

Hung Tien Bui, Yuke Wang, and Yingtao Ji
ang,
Member
,

IEEE


I. I
NTRODUCTION


In today’s world there is an increasing demand for small portable electronic
devices. Most people using cell phones, laptops, and palmtops would not want to carry a
cumbersome power supply around with them; therefore, t
hese devices require low power
microelectronics. Low
-
power design has become an integral part of modern electronics
and much research has gone into designing faster, more efficient circuitry.


An
arithmetic
-
logic unit (ALU) is the part of a computer proc
essor that performs

arithmetic and logic operations, and the full adder circuit is the part of the ALU that sums
binary bits (1’s and 0’s). Hung Tien Bui, Yuke Wang, and Yingtao Jiang propose 41
newly designed adders that consume 10% less power and are 9
0% faster than previous
technology. I will summarize their article published in IEEE
Transactions on Circuits and
Systems
-
II: Analog and Digital Signal Processing VOL. 49, NO. 1, JANUARY 2002


II.

L
OW
P
OWER
F
ULL
A
DDERS


Binary addition is quite simple, th
ere are only three different cases: 0 + 0 = 0, 1 +

0 = 1, 1 + 1 = 10. You will notice the binary bit furthest to the right, also known as the
least significant bit (LSB), is a “0” if the two numbers being added are the same. The
LSB is a “1” if the number
s are not the same. In binary operations, the only two
possibilities are “1” and “0”. This reasoning posits the use of
XOR

and
XNOR

gates to
perform binary addition. The
XOR

and
XNOR

gates take two inputs and produce a single
output. The
XOR
produces a “0”

if the two inputs are the same and a “1” if they are
different. The
XNOR

produces the exact opposite of the
XOR
.




Transistors are used to construct
XOR

and
XNOR

gates that make up the adders in
the ALU, and electronic signals of around 5 volts and 0 vol
ts are used to indicate a “1”
and a “0” respectively. As the signals pass through the transistors, power is consumed
and time passes. It only makes sense then that using fewer transistors will take less time,
and require less power. The smallest
XOR
-
XNOR

g
ates (gates that use the least amount of
transistors) have four transistors. Hung Tien Bui, Yuke Wang, and Yingtao Jiang propose
a new design for these gates also using only four transistors. The new designs have no
direct connection to ground and are ther
efore called
groundless

XOR
-
XNOR

gates.



Computer software allows us to simulate circuits and observe results as they
would happen in real applications. The majority of the article discusses the simulations
and tests done to the new 10
-
transistor adders.
Each circuit was simulated using HSPICE
on an Ultra
-
SPARC 2 machine. HSPICE is a widely used simulation tool for accurately
modeling integrated circuits.



Different circuits respond differently to different input patterns. Six different
patterns were use
d to cover all possible input pattern combinations. Each pattern was
simulated twelve times using a range of frequencies from 50kHz (fifty
-
thousand cycles
per second) to 200MHz (two hundred million cycles per second). Finally, three different
capacitor val
ues were used to test the circuit under different load conditions. 216
simulations were made for each of the new adders, making the total number of
simulations in the preliminary part of the experiment equal to 9288.



After the simulations, three of the
new adders stood out as being the best. The
article referred to these adders as “adder 9A”, “adder 9B”, and “adder 13A”. Now for a
comparison with current technology, more simulations needed to be made. Along with a
SERF adder (
Static Energy
-
Recovery Full
-
Adder) and a CMOS (Complimentary Metal
-
Oxide
Semiconductor) adder, t
hese five adders were then put through an additional 3960
simulations.


III.
S
UMMARY


Adder 9B consumed 12% less power than the SERF adder. Adder 9A and 13A
had better power consumption

except when the load capacitance is 0.01pF. Adder 9A
consumes 20% less power and 13A consumes 10% less power. The CMOS adder
consumed more power than even the SERF adder. Adder 13A and 9B are 93% faster than
the SERF adder. This article has shown that thr
ee of the 41 new 10
-
transistor adders have
proven to be faster and more efficient than current technology and also have proven to be
good designs for future high performance microelectronics.