Critical Summary of CMOS Transconductance Multipliers: A Tutorial

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1



Abstract
--

A critical summary of [1]
,

which
act
s

as a
comprehensive
tutorial on CMOS transconductance
multipliers,

is presented.

Real
-
time analog multiplication of two

sign
als is one of the most important operations in analog signal
processing [1].

[1]

provides a complete survey of CMOS
multipliers, classifies them into appropriate categories, and
proposes the most recommended MOS multiplier structure
.
Firstly introduction a
nd summary of the contents of the paper
are presented. Next the methods used and results obtained in
the paper are presented. This is followed by conclusion and
significance of the paper. Finally the follow
-
on research that
could be performed in the area o
f research of the
paper and
paper’s relation to author’s

field of study are presented.


I.

I
NTRODUCTION

ULTIPLIERS perform linear products of two signals
x

and
y

yielding an output
z

=
Kxy

where
K

is a


multiplication constant
with suitable dimension

[
1]
.



Fig. 1. Basic idea of a multiplier


Figure 1 from [1], shows the basic idea of the multiplier
implementation. Two signals,
v
1
(
t)

and
v
2
(
t
), are applied to a
nonlinear device, which can be characterized by a high
-
order
polynomial function. This poly
nomial function generates
many
undesired
terms
besides the desired
v
1
(
t
)
v
2
(t).
These undesired
terms need to be cancelled. This is accomplished by
a
nonlinearity
cancellation circuit configuration.

II.

SUMMARY

A multiplier could be realized using programmable

transconductance components [1]. Figure 2 shows a multiplier
realized from three transconductance components
, where
output current is a product of two input voltages v
1
and v
2
.
Two of these components have the same transconductance


Gm
1

and third one has
Gm
2
. The third transconductor Gm
2

acts
as nonlinearity cancellation circuit configuration.



Fig. 2 Multiplication operation using programmable
transconductor


TABLE I

SUMMARY OF MULTIPLIER OPERATING MODES


Critical Summary of CMOS Transconductance
Multipliers: A Tutorial

Chirag Sharma

M



2



In [1],
authors classify transconductor multip
liers

into eight
types
. They are broadly classified into two groups based on
their MOS operating region, i.e.
linear region

or saturation
region.
They can be further classified based on their
nonlinearity cancellation schemes and signal injection method.
T
able I summarizes these results.


Fig. 3
. Four
-
quadrant multiplier basic architectures. (a) Using
single
-
quadrant multipliers. (b) Using square devices.


Only two cancellation methods for the four
-
quadrant
multiplication are known [1]. Since a single
-
end
ed
configuration cannot achieve complete cancellation of
nonlinearity and has poor power supply rejection ratio (PSRR),
a fully differential configuration is necessary in a sound
multiplier topology. The multiplier has two inputs, therefore
there are four
combinations of two differential signals, i.e.



and
.

The topology of
Fig. 3(a) is based on single
-
quadrant multipliers. Fig. 3(b) is
based on square
-
law devices.
These topologies achieve
multiplication and simultaneously cancel out all the higher
order and common
-
mode components (
and
) based on
the following equalities:





(1)

or



(2)

respectively. The lower case letters in above equations
represent small signals.


MOS transistors can be used to implement cancellation
schemes given by (1) and (2) and the fundamental operati
on is
a transconductance multiplier be
cause the MOSFET is a
transconductance device. The simple MOS transistor model is
expressed as


for

(3)


for


(4)

for NMOS FET in its linear and saturation regions,
respectively.


and
stand for
transconductance parameter and threshold voltage of the MOS

transi
stor[1].

The terms

in (3),

in (3
),

or

in (4)
can be

used to implement (1) and (2) respectively.

III.

M
ETHODS AND
R
ESULTS

Most of the performance measures for the multipliers are
strongly a
pplication dependent, so the authors in [1] examined
all the eight types of multipliers in Table I qualitatively. After
this qualitative study they kept only five multipliers for further
analysis, rejecting rest others

because of their disadvantages
.
Multi
pliers of Type I
given in [
2
] require additional circuitry.
Multipliers of Type II, Type III, and Type IV

require additional
circuitry and have poor linearity. Multiplier of Type V given in



3

[3
] requires an op
-
amp.
Multipliers of Type VI have poor
linearity
. Multipliers
of Type VII

require additional circuitry.
Multipliers of Type VIII are based on Gilbert cell [
4
], and
require high power supply
voltage and have poor linearity
.

The five multipliers selected qualitativel
y are given in [5], [6],

[7],

[
8]

and
[9]
.

These five multipliers were designed without
optimizing a specific performance for a rough comparison
through simulation.
All the multipliers had transistors of same
dimensions and were subjected
to dc analysis, power analysis
and
Monte Carlo analysis
.

Multipliers given in [5] and [8] were
considered to have better performance than others
. The
multiplier in [6] has low transconductance, high sensitivity to
device
mismatch and poor linearity. M
ultiplier in [7] is sensitive

to device mismatch and has lo
w transconductance. Multiplier
in [9] consumes high power and has poor linearity.

The authors in [1] did a detailed linearity simulation on
multipliers given in [5] and [
8
]. In multiplier given by [5],
linearity improves by making the source follower trans
istors
wider
, while that is not the case with multiplier in [
8
].

The
authors fabricated multipliers given in [5], [6] and [
8
] in a 2 µm
N
-
well process.
The linearity errors in multiplier given in [5]
were less than the other two.
The authors in [1] analyti
cally
show that multiplier in [5] needs lower power supply voltage
than the one in
[8
] for the same input range for both the inputs.
The authors in [1] experimentally calculated the noise floor in
multiplier given by [5] to be 26 dB lower than the one in
[
8
].

Finally, the authors in [1] propose the multiplier in [5] as the
most recommended analog MOS multiplier structure

and
discuss design considerations for it
.
The multiplier given in [5]
has a tradeoff between noise and linearity [1]. The authors in
[1] e
xperimentally found out that the optimal ratio of
transconductance of transistor in saturation (K
2
) to the
transconductance of linear region (K
1
) is around three for low
-
noise design in the recommended multiplier.

They also found
that for low noise design
the input range of the recommended
multiplier has to be sacrificed.

IV.

CONCLUSION AND SIGNI
FICANCE

The authors in [1] were able to categorize

most of the

transconductance multipliers into eight categories.
The
multiplier recommended by [1] is a good choice f
or low voltage
low power designs.

This is a very useful paper as it quickly presents an
overview of all important transconductance multiplier
topologies

to a designer so that he can chose the optimal
topology for his specific application and confirming
de
sign
specification
.

The paper was very superficial about the
topology it recommends since it does not provide
much detail

about its maximum frequency of operation
which is important
for a high
-
performance design.

V.

FOLLOW
-
ON RESEARCH

Nowadays there is a
grea
t impetus to fabricate high
-
performance mixers on CMOS process used for digital designs.

Follow
-
on research
could involve coming up with a tutorial for
CMOS transconductance multiplier optimized for various
performance parameters like minimum power supply

voltage,
maximum frequency range etc.

VI.

RELATION TO FIELD OF

STUDY

The paper being reviewed is strongly related to reviewer’s
field of study and research. The reviewer is currently working
on a low
-
power mixed
-
signal integrated circuit to detect faults
on
aircraft wiring. This integrated circuit
needs a multiplier to
perform correlation between two signals. Since one of the
signals is a square wave, even a mixer would be sufficient for
the job.

Still, t
he multiplier recommended by [1] is a good
standard t
o compare against

the mixer to be designed.

R
EFERENCES

[1]

Gunhee Han and Edgar Sanchez
-
Sinencio
, "
CMOS
Transconductance

Multipliers: A Tutorial
,"
IEEE Trans.
Circuits Syst.
II:

Analog and

Digital Signal Processing, vol.45
,

no. 12
,

pp.
1
5
50
-
1
5
63
,
Dec
. 19
98
.

[2]

B.

S. Song,
“CMOS RF

circuits for data communications

applications,”
IEEE J. Solid
-
State Circuits
, vol. SC
-
21,

pp. 310
-
317
, April 1986.

[3]


Z. Wang, “A four
-
transistor four
-
quadrant analog multiplier
using MOS transistors operating in the saturation region,”
IE
EE
Trans. Instrum. Meas
. , vol. 42, pp. 75
-
77, Feb. 1993.

[4]

B. Gilbert, “A precision four
-
quadrant multiplier with
subnanosecond response,”
IEEE J. Solid
-
State Circuits
, vol. SC
-
3, pp. 353
-
365, Dec. 1968.

[5]

S. Liu and Y. Hwang, “CMOS four
-
quadrant multiplier
using
bias feedback techniques,”

IEEE J. Solid
-
State Circuits
, vol. 29,
pp. 750
-
752, June 1994.


[6]

C. Kim and S. Park, “New four
-
quadrant CMOS analogue
multiplier,”
Electron. Lett
., vol. 23, pp. 1268
-
1270, Nov. 1987.

[7]

A. Diaz
-
Sanchez and J. Ramirez
-
Angulo, “
Design and
implementatio
n of VLSI analog adaptive filters,” in
Proc. IEEE
Midwest Symp. Circuits and Syst
. Aug. 1996, pp. 1366
-
1368.

[8]

H. Song and C. Kim, “An MOS four
-
quadrant analog multiplier
using simple two
-
input squaring circuits with source followers
,”
IEEE J.

Solid
-
State Circuits
, vol. 25, pp. 841
-
848, June 1990.

[9]

Y. Kim and S. Park, “Four
-
quadrant CMOS analogue
multiplier,”
Electron. Lett
., vol. 28, pp. 649
-
650, Mar. 1992.