CPT 310 Logic and Computer Design

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15 Νοε 2013 (πριν από 3 χρόνια και 10 μήνες)

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CPT 310




Logic and Computer Design

Instructor: David Lubliner



Phone 973.596.2878

email : robot1@adm.njit.edu

Engineering Technology Dept.



Cell 201
-
960
-
8018 (important) M
-
F 10
-
5PM

Text: Logic & Computer Design Fundamentals: 3
rd

Edition

M. Morris Mano & Charles Kime (Software included with text XiLinx version 6.3i)

Pentium 4

1)
1 MB L2 Cache

2)
Floating Point Unit

3)
Schedulers

4)
Allocator

5)
Arithmetic & Logic Unit

6)
16 KB Data Cache

7)
Microcode rom

8)
Trace Cache

9)
Data Translation Buffer

10)
Brach Perdition Unit

11)
Instruction TLB

Memory

Diagram pg 6 text

CPU

Control

Unit

Data

Path

Input / Output

10101010

11011011

Basic Architecture & Logic

Course Summary

Detailed Understanding Computer
Design

Grading
-

CPT 310


Midterm Exam


25%


Final Exam


25%


Homework


50%


Exercises at the end of chapter


XiLinx Software: schematic editor


Course Summary


The object of this course is to provide an understanding of the fundamentals of logic and computer design. The first half cov
ers

logic design; number
systems, Gates, mapping (Karnaugh maps), arithmetic and sequential circuits and the second half covers digital system design;

ar
ithmetic and logic unit
(ALU), sequential control design and communication between CPU and i/o devices. The course provides digital system design fun
dam
entals while
taking a gradual bottom up development of the fundamentals.


Schedule


Week


1
st


9/7

Course Introduction


2
nd


9/14

Binary numbers/Arithmetic Operations/BCD/Gray codes/ASCII


3
rd


9/21

Combinatorial Logic Circuits Part I / XiLinx Schematic editor Part I


4
th


9/28

Combinatorial Logic Circuits Part 2/ XiLinx Schematic editor Part2 I


5
th


10/5

Combinatorial Logic Design / Hierarch and top down design


6
th


10/12

Combinatorial Functions and Circuits


7
th


10/19

Programmable Logic arrays & devices/Decodes/Multiplexers


8
th

Midterm10/26


9
th

11/2

Arithmetic functions & circuits


10
th

11/9

Sequential circuits


11
th

11/16

Registers and Register Transfers


12
th

11/23

Sequencing & Control


Thanksgiving 24
th

& 25th


13
th

11/30

Computer Design Basics/Instruction set architectures


14
th

12/7

Input
-
Output and Communications


Reading Days 12/14


15
th
Final

12/21


Course Overview

Chapter 1: Digital Computers and Information

Illustration at beginning of each Chapter

Base 10

Binary Base 2


Octal Base 8


Hex bas 16

08 1000 10 8

15 1111 17 F

BCD Binary Coded Decimal

4 bit code represents number 0
-
9

Base 10

BCD

0


0000

1


0001

9


1001

-
Addition

-
Subtraction

Parity Bit
(checks for transmission errors


Checks if total number of bits is even or odd

Number

even parity

1000001

0
1000001

1010100

1
1010100

Course Overview

Chapter 2: Combinatorial Logic Circuits

Illustration Pg. 32

Logic Circuit Diagrams

-
Circuit Optimization
-
2,3,4 level maps

48 elements

Optimized to 25

Clock pulses
are used
instruct
components
(gates, etc. to
perform the
next operation)

Maps used to optimize circuits






XY

XY

XY

XY

0

1


0 1

X

Y

1

0

1


0 1

X

Two Var Map

Ex: XY

Y

Xilinx Design & Simulation Software

Course Overview

Chapter 3: Combinatorial Logic Design

Combinatorial Logic Circuit Diagrams

-
Programmable Implementation Devices

Design Hierarchy
reduces the complexity

required to represent the schematic diagram of
a circuit

Combinatorial

Circuit

N Inputs

M Outputs

Components

Represents
the function
of these
circuits

Course Overview

Chapter 4: Combinatorial Functions and Circuits

Fundamental circuits
decoders
, encoders,
code converters, multiplexers and
programmable logic, which are building blocks
for larger circuits and systems.

Sequential Circuit

Combinatorial


circuit

Inputs

Storage


Elements

Next State

Outputs

Present
State

Decoding

An
n bit code

is capable of representing 2
n

distinct elements

Pg 148

CPU

Cache

Main

Memory

Course Overview

Chapter 5: Arithmetic Functions and Circuits

The concept of
iterative circuits

made up of
arrays of combinatorial

cells is introduced.
Blocks designed as iterative arrays for
performing addition, subtraction and
multiplication are covered


Two’s Compliment. ( Subtract by adding )


Carry Look Ahead Adder ( pg 206 )

Iterative Circuit

Operates on two n
-
input input vectors and produces an n
-
output vector

Pg 202

4
-
bit Ripple Carry Adder

Course Overview

Chapter 6: Sequential Circuits

In order to perform useful of flexible sequences
of operations we need to be able to construct
circuits that can
store information between

operations
.

Such circuits are called
sequential circuits

SR Latch with NOR gates

Synchronous clocked Sequential Circuit

S
et
-
R
eset

Pg 244

The most basic storage elements are latches, from which flip
flops are constructed

J
-
K Flip
-
Flop

S

R

Clk

Q

Q

S R Qn+1

1 0 1

0 1 0

0 0 Qn

1 1 Qn

Course Overview

Chapter 7: Registers and Register Transfers


Registers

are particularly useful for
storing
information

during the processing of data and
counters assist in sequencing the processing.


A
data path
consists of processing logic and a
collection of registers that perform data
processing.


A
control unit

is made up of logic that
determines the sequence of data processing
operations performed by the data path


4 Bit Register

Pg 316

Block Diagram of Registers

Course Overview

Chapter 8: Sequencing and Control

The focus of this chapter is the
control unit
.
Digital systems can be classified as
programmable or non
-
programmable systems
depending on the type of control unit.

Non
-
programmable systems have inputs but
do not have any mechanism for executing
programs.
The focus of this chapter is
non
-
programmable systems
, primarily using a
multiplier.

Programmable systems covered in chapter 10

The control unit
determines the operations
to be performed

and the sequence of those
operations
based on its inputs and the
status bits

from the data path.


Control Unit for Binary Multiplier

Pg 316

State Table for sequence register and decoder part
of multiplier control unit

Course Overview

Chapter 9: Memory Basics

Random access memory (RAM) stores data
temporarily.

Read only memory (ROM) stores memory
permanently. ROM is one form of a variety of
components called programmable logic devices
(PLDs) that use stored information to define logic
circuits

There is
Internal Cache

and
external RAM
.


Block diagram of 256K by 8 RAM

Pg 412

Symbol for 64K x 8 RAM chip

Decoder: 2 input bits select 1
-
4 RAM chips

Course Overview

Chapter 10: Computer Design Basics

The generic data path combined with a control
unit and memory forms a
programmable
system
, in this case, a simple computer.

An
Instruction Set Architecture (ISA)

combines
control unit, and generic data path are combined
to form a CPU (Central Processing Unit). In
Programmable units memories are present for
storage of data and programs




Block Diagram of a generic data path

Symbol for n
-
Bit ALU Arithmetic and Logic Unit

Pg 433

Discuss Current Architectures